Verification and Validation of Standard Cell Scan C-element in Prototype Chip

Abstract

It is most important to conduct high quality testing on manufactured asynchronous circuit LSI if asynchronous circuits are to become widely used. The solution to this problem is to employ scan design, in which the full scan design of synchronous circuit is applied to asynchronous circuit. The scan design entails the replacement of sequential elements with corresponding scan elements. C-element is the most popular utilized sequential elements in asynchronous circuits, and scan C-element is proposed for scan element adapted C-element. Moreover, we proposed standard cell scan C-element enable using automatic placing and routing. As LSI become more highly integrated, automated placing and routing tools are indispensable for design. However, the proposed standard cell scan C-element has not been verified on a chip, and their operation has not been validated. In this paper, the area overhead of the standard cell scan C-element is evaluated. Furthermore, the standard cell scan C-element was integrated into a prototype chip, and its functionality and delay overhead were verified and validated through oscilloscope analysis. Consequently, it was demonstrated that the standard cell scan C-element operates to specifications with a smaller area and smaller delay overhead than conventional scan C-element.