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IPSJ Transactions on System LSI Design Methodology
Vol. 6 (2013) pp. 122-126



For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology.

Copyright © 2013 by the Information Processing Society of Japan

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