IPSJ Transactions on System LSI Design Methodology
Online ISSN : 1882-6687
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks
Yuko Hara-AzumiToshinobu MatsubaHiroyuki TomiyamaShinya HondaHiroaki Takada
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2013 Volume 6 Pages 122-126

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Abstract

For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology.

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© 2013 by the Information Processing Society of Japan
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