IPSJ Transactions on System LSI Design Methodology
Online ISSN : 1882-6687
ISSN-L : 1882-6687
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits
Taiga TakataMasayoshi YoshimuraYusuke Matsunaga
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2013 Volume 6 Pages 127-134

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Abstract

This paper presents two acceleration techniques of fault simulation for analyzing soft error propagation in sequential circuits. One is an exact technique and the other is a heuristic technique. Since these techniques are independent on how the logic functions of circuits are evaluated, they can be combined with other techniques which accelerate evaluations of the logic functions of circuits, such as event-driven simulation, single pattern parallel fault propagation (SPPFP). Experimental results show that applying the exact technique makes a fault simulator with event-driven simulation and SPPFP 30-143 times faster. A fault simulator with the exact technique finished for several large-scale circuits in 4.6 hours or less, while a fault simulator without the exact technique could not finish for such circuits in 72 hours. Furthermore, applying the heuristic technique makes a fault simulator with the exact technique about 7-17 times faster with only 0.5-2.2% estimation error.

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© 2013 by the Information Processing Society of Japan
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