IPSJ Transactions on System and LSI Design Methodology
Online ISSN : 1882-6687
ISSN-L : 1882-6687
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays
Yoshinobu HigamiSenling WangHiroshi TakahashiShin-ya KobayashiKewal K. Saluja
Author information
JOURNAL FREE ACCESS

2016 Volume 9 Pages 13-20

Details
Abstract
For the purpose of analyzing the cause of delay in modern digital circuits, efficient diagnosis methods for delay faults need to be developed. This paper presents diagnosis methods for gate delay faults by using a fault dictionary approach. Although a fault dictionary is created by fault simulation and for a specific amount of delay, the proposed method using it can deduce candidate faults successfully even when the amount of delay in a circuit under diagnosis is different from that of the delay assumed during the fault simulation. In this paper, we target diagnosing the presence of single gate delay faults and double gate delay faults. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed methods.
Content from these authors
© 2016 by the Information Processing Society of Japan
Previous article Next article
feedback
Top