Abstract
A congestion-driven placement technique for LSI cells through hybrid genetic algorithm is presented. In particular, the procedure consists of a two-level hierarchical placement procedure and a hybrid genetic algorithm, in which the algorithm is combined with the approach of searching locally for an optimal solution. For selection control, new objective function are introduced to each phase for dispersing congestion, and a parallel processing technique suited to hierarchical placement is proposed as an effective approach to accelerating the processing speed of genetic algorithm-based placement. Regarding to total virtual wire length and wire congestion, the ratio of the proposed approach to the conventional one is 0.76 and 0.9, respectively. As a result, the effectiveness of the suggested approach is shown through a comparison with the conventional one.
