2003 Volume 16 Issue 9 Pages 439-450
The performance of the Cell Array's structure for the Dynamically Reconfigurable Cell-Array Processor (DRCAP), which we first proposed in 1997, in actual program execution is examined. In the DRCAP, the processing of c-language program sentences, such as “if” and “for”, is remarkably accelerated by applying the pipeline or the parallel operation to repeating calculations. The performance of the Cell Array's structure in actual program execution is evaluated for the MPEG de-quantization process. It is found that a processing rate 30 times as higher as those in the conventional microprocessors can be realized in the present DRCAP.