Abstract
SRIF (Square Root Information Filter) is a method of solving for optimum estimate in the least square sense. SRIF finds optimum estimate by updating a square root matrix of an information matrix. In the paper, a new VLSI systolic array for SRIF parameter estimation is proposed. SRIF parameter estimation consists of orthogonal transformation and solving linear equations. The method that solves SRIF parameter estimation by use of Givens rotation and back substitution was proposed. But it is well known that complete pipelining of these two separate algorithms is impossible. To avoid this problem, we propose a new method of using the Faddeeva algorithm instead of back substitution. The Faddeeva algorithm is performed by Gauss elimination. Pipelining Givens rotation and Gauss elimination is now feasible as parallel architecture. Making use of this method, we constitute a high-speed VLSI systolic array for SRIF parameter estimation than a conventional one.
