10-3 A Low-Noise Transistor and Column-Parallel Readout Circuit for CMOS Image Sensors and Noise Reduction Effects

Min-Woong Seo; Keita Yasutomi; Keiichiro Kagawa; Shoji Kawahito

doi:10.11485/iteac.2013.0_10-3-1

PROCEEDINGS OF THE ITE ANNUAL CONVENTION

Online ISSN : 2424-2292
Print ISSN : 1343-1846
ISSN-L : 1343-1846

2013

Session ID : 10-3

DOI https://doi.org/10.11485/iteac.2013.0_10-3-1

Conference information

Name : 2013 ITE Annual Convention

Location : [in Japanese]

Date : August 28, 2013 - August 30, 2013

10-3 A Low-Noise Transistor and Column-Parallel Readout Circuit for CMOS Image Sensors and Noise Reduction Effects

Min-Woong Seo, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito

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CONFERENCE PROCEEDINGS FREE ACCESS

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Abstract

A CMOS image sensor with a low noise transistor is developed. The proposed imager has a low vertical fixed pattern noise (vFPN) and small random telegraph signal (RTS) noise because of the noise reduction effect of the native transistor as an in-pixel source follower amplifier.

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