Process Compensation Techniques for Low-Voltage CMOS Digital Circuits

Abstract

In low-voltage CMOS digital circuits, the threshold voltage variation causes significant circuit performance fluctuation: we therefore propose on-chip process compensation techniques for such circuits. We used voltage reference circuits, that can monitor process variations. We confirmed the operation of the circuit by using a SPICE simulation with a set of 0.35-μm standard CMOS parameters, and we performed Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs. SPICE simulation demonstrated that the process variations of digital circuits were improved by 45% after applying the proposed architecture. These techniques will be useful for the on-chip process compensation of low-voltage digital circuits.