Surface Defect Inspection System for VLSI Wafer

Abstract

This paper proposes an automatic identification method of surface defects on the VLSI wafer (which has repeated patterns on each chip). The applied system of this method is described, using a VLSI wafer as an example of its practical use. This inspection system utilizes boundary extraction with improved S/N ratio, and a defect detection algorithm obtained by matching two corresponding parts of these repeated pattern boundaries.
Making high speed the circuitry of the above process, this system can be put to practical use.