A Parallel Architecture for Intelligent Image Sensors Using Floating Gate Transistors

Abstract

A parallel architecture is proposed for fast spatial filtering operations using floating gate transistors with differential inputs and feedback. Arbitrary signed convolutions can be performed in a completely parallel manner with the proposed architecture. Only one terminal is required for the feedback which is capable of suppressing the distortions caused by active elements. This architecture is also suitable for other operations including DFT/DCT. In particular, if 2D-DCT is implemented with this architecture together with an array of photosensors, an image compression sensor can be developed.