Abstract
We consider the LSI circuit of the multirate discrete cosine transform (MR-DCT) that can realize a simple and fast image compression. The MR-DCT uses only additions and subtractions except for one multiplication of mean operation, but needs the compensation operation. For the fast operation that is one clock for one DCT coefficient we propose the heuristic MR-DCT (HMR-DCT) and for a simple LSI circuit we present an approximate HMR-DCT with equivalent sampling. The realization of a 9×9 block DCT hardware that is a basic element for the image compression circuit is considered and simulated by the circuit simulator.
