Abstract
This paper describes the design and the implementation of a CMOS image sensor integrating focal-plane compression using an analog 2-dimensional discrete cosine transform(2-D DCT) processor and variable-quantization-level A/D converter. The proposed focal-plane compression scheme is particulary useful for high-speed cameras and low-cost, low-power portable cameras. The PSNR of time reconstructed image using the on-sensor analog 2-D DCT circuits is 36.7dB. The power dissipation of the analog 2-D DCT circuits is about 10.8mW at 3V. The total one-chip camera system power is estimated to be about 30mW, allowing us to use for portable devices.
