Abstract
A new digital camera architecture has been developed which utilizes the advantages of isochronous data transfer available in many new emerging bus structures such as IEEE-1394 and USB. This design eliminates the need for a digital frame memory, typically used with other architectures, by utilizing the inherent analog memory of a FT CCD. The key element of this design is a video line circulating FIFO, which allows the CCD to operate in a single register readout mode. This FIFO reduces the overall complexity of the analog interface circuitry while still providing advanced functions such as image resolution scaling, vertical aperture correction, and other image processing algorithms. The details of this architecture are presented in this paper.
