An area-splitting parallel signal processor for a very-high resolution image acquisition system

Abstract

An area-splitting parallel signal processor for a very-high resolution image acquisition system is developed. In order to realize a high-speed processing, acquired image data is devided into twenty four VGA-class images. The processor is also designed to be flexible with imager pixel counts or system requirements. A 4K×2K pixel color acquisition system with four progressively-scanned-two-million-pixel CCD imagers is developed, and an enhancement circuit is implemented with this processor.