A High-Speed and Low-Power AD Converter Using Folding Technique
Details
A high-speed and low-power piplined analog-to-degital (AD) converter using folding technique is proposed. Comparing with existing folding AD converters, the proposed AD converter operates at a higher sampling frequency due to pipline operation and dissipates lower power due to small scale circuits thanks to selecting only necessary interpolation source signal. The AD converter was designed with 0.35um CMOS technologies. We have good outlook for realizing a 6bit AD converter which can operate with a power dissipation of about 120 mW at 200MS/s by circuit simulation.
