MPEG-2 Video Decoder Using VLIW Based Media Processor

Abstract

We have developed the All Format Decoder (AFD), which is an MPEG-2 Video Decoder for the Digital Television using the MAP-CA media-processor based on the VLIW architecture. The down-sampling algorithm of AFD enables us to reduce the amount of necessary memory and processor power. By efficient use of SIMD instructions, the DMA engine, and the Co-Processor for variable length decoding of the MAP-CA, the AFD can decode the video stream of 1080i format with only 3.5MB memory at 270MHz of the CPU clock.