Chip Level Substrate Noise Analysis Method with Substrate and Digital Noise Injection Models

Abstract

We developed a substrate noise analysis methodology employs chip-level substrate modeling based on F-matrix computation and digital substrate-noise injection modeling with the time-series divided parasitic capacitance model. The methodology enables rapid and reliable estimations of substrate noise waveforms. And substrate noise waveforms for 0.6μm CMOS 4.5mm square chip with practical digital circuits are simulated and compared with measurements with a 100ps - 100μV resolution. Peak to peak substrate noise amplitudes are roughly with the average error of 10% compared with measurements for conventional as well as reduced substrate noise designs.