A Hardware Architecture for an Affine-Based Motion Estimation
Details
This paper proposes an architecture for an affine-based motion estimation algorithm. Although an affine-based motion estimation algorithm can estimate accurate motion from image sequences, it requires high computational power. In order to avoid such computational complexity, we propose a hardware architecture for the motion estimator. Furthermore, we propose a method to achieve high throughput and low hardware complexity in the motion estimator. In this paper, we describe the motion estimator in VHDL and then show the result of design using an EPGA.
