MPEG2 HDTV Video decoder

Abstract

HDTV video processor capable of decoding and displaying two streams simultaneously has been developed. This video processor includes MPEG2 MP@HL decoder, TS decoder, video display controller, and SDRAM controller. High throughput pipelining technique, efficient parallel data bus structure, efficient method to reduce amount of frame memory which required to decode 2ch HD stream simultaneously. By this function, we have realized a reasonably priced digital television with which you can enjoy an increased variety of program content. This video processor includes 5.7 million transistors and is manufactured of 0.18 μm process and the chip size is 6.86mm × 6.86mm, the power consumption is 0.8W.