A 1/2.5-in 8M CMOS Image Sensor with a Staggered Shared Pixel Architecture and an FD-Boost Operation

Abstract

A 1/2.5-in 8M CMOS image sensor employs a staggered shared pixel architecture in order to suppress Gr/Gb sensitivity imbalance. It also employs an FD-boost operation using both CGS and CGD of amplifier transistor to make possible both low dark random noise and large FD capability. It achieved Gr/Gb sensitivity ratio of 99.7%, random noise of 2.6e- and pixel capacity of 7.7ke-.