Settling Time is a primary design parameter in operational transconductance amplifiers (OTAs) used for high-speed applications such as pipeline A/D converters. For scaled CMOS technologies, an OTA design methodology using g_m/I_D lookup tables has been proposed to minimize its power consumption. A major problem in the conventionally proposed method is that Settling Time was not included in a target specification, but was converted into crossover frequency f_c with an empirical approach. In this paper, we introduce an iterative optimization sequence to design OTAs, which can achieve the target Settling Time with the minimum power consumptions.
