High-Speed Ramp-Wave Generator with Interleaved DAC for Single-Slope ADC
Details
We have proposed the method of re-measuring quantizing error of Single-Slope ADC for CMOS imager with TDC (Time-to-Digital Converter). Using n-bits TDC, the proposed ADC performed 2^n time faster operation. This method requires high-speed Ramp wave generation. Therefore, in this paper, we evaluated speed up with interleave operation and output summing of DACs. Although multiple DACs are used, there is no increase of quantization unit devices. In the interleaved DAC with 2^<n-m> of m-bits DACunits, it can perform as a Delta DAC (-2^1≦ΔVout≦2^<m-1>). We designed the current-controlled DAC circuits using 0.25um CMOS process. At 200-MHz-clock operation, we confirmed 800-MHz 12-bit operations with four of 10-bits DACunits.
