Abstract
A 256x256 CMOS imager with column-parallel ΔΣADCs and built-in single-shot compressed sensing performed during A/D conversion is fabricated in 0.15μm CIS process. Compression ratios of 1/4, 1/8, and 1/16 can be programmably achieved at 480, 960, and 1920fps, respectively, with the same readout noise of 351μV_<rms> and power consumption of 96.2mW as normal 120fps capture and with minimal die area overhead. Image reconstruction performed off-chip shows modest quality loss relative to normal capture.
