A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters

Abstract

A 1.1μm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based ADC has been developed. The hybrid-stacking technology connects the pixels and an arrayed ADC in the pixel area. The pipelined operation of the cyclic-cyclic-SAR ADC effectively reduces the conversion time period to 0.92 μs. The ADC architecture and the hybrid-stacking technology achieve a high frame rate of 240 fps in 33 Mpixels. A random noise of 3.6 e- and sensor power consumption of 3.0 W are attained at an extremely high pixel rate of 7.96 Gpixel/s.