Record of Joint Conference of Electrical and Electronics Engineers in Kyushu
Record of 2011 Joint Conference of Electrical and Electronics Engineers in Kyushu
Session ID : 09-1A-04
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Host: Joint Conference of Electrical and Electronics Engineers in Kyushu

Design of circuit that decreases with threshold variation in FG-MOS inverter circuit used for four-valued half adder
Yuya Wada, Shinpei Sakaguti, Sumio Fukai, Akio Shimizu
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[in Japanese]
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© 2011 Committee of Joint Conference of Electrical and Electronics Engineers in Kyushu
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