Effects of Wafer Cleaning on the Interconnect Structure and Its Electrical Properties during the Al Dual Damascene Process for the Fabrication of Sub-100 nm Memory Devices

Abstract

An Al dual damascene process for the metallization of sub-100 nm dynamic random access memory devices was performed, and the effects of wafer cleaning method on the damascene structures and their electrical properties were investigated. Interconnect structures obtained with the Al dual damascene process using the conventional NH₄OH-based wet cleaning (Type I) and the wet cleaning followed by CF₄/Ar-plasma dry cleaning (Type II) showed that the metal lines having the aspect ratio of 3 were patterned without gap-filling of inter metal dielectrics. All the sheet resistances of metal lines using the two different wafer cleaning methods during the Al dual damascene process were within specification. The via resistance distributions, however, depended on the cleaning method, and it was found that the cleaning Type II produced a 100% yield and very narrow distribution of the contact resistances of the 0.24 μm-diameter via due to the efficient removal of stable Al_xO_y species for cleaning Type II.