Multi-Loop PID Controllers Design for MIMO Processes Containing Integrator(s)

Abstract

In this paper, design of multi-loop PI/PID controllers for an MIMO process which contains pure integrators and dead times is presented. A modified RGA is proposed to overcome the difficulty encountered in computing the RGA of the integrating process for loop pairing. After loop pairing, the design of N-loop controllers is decomposed into the design of N effective loops. From the controllers of these effective loops, multi-loop PI/PID controllers are determined. Each controller of the effective loops is derived from an equivalent system having cascaded loops. A method for synthesis of such controllers consists of two major steps. As a first step, a robust open-loop stable process is obtained by closing inner loops around those integrating processes. The controllers in the inner loop are aimed at good stability robustness without too much concern on the performances. For this reason, synthesis of these controllers is much easier. Then, in the second step, multi-loop controllers are designed to cascade those inner loops with emphases on both performance and robustness. The controllers obtained in the two steps are then used to derive the final multi-loop SISO controllers. Numerical examples are used to illustrate the design and the performances of the proposed design method.