TEION KOGAKU (Journal of Cryogenics and Superconductivity Society of Japan)
Online ISSN : 1880-0408
Print ISSN : 0389-2441
ISSN-L : 0389-2441
Focused Reviews
Fabrication Process for Low-Tc Superconductor Electronics Devices and Its Future Prospects
Mutsuo HIDAKA, Shuichi NAGASAWA
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2017 Volume 52 Issue 5 Pages 315-322

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Abstract

We are routinely fabricating many superconducting digital devices using three types of Nb-based fabrication process. One of them consists of nine Nb, one Mo and one Nb/AlOx/Nb Josephson junction (JJ) layers. Controllability in the device parameters, such as the critical current density (Jc) of JJ, has been improved. Jc in the Nb 9-layer process was controlled within ±10% of the 10 kA/cm2 target value for all 18 wafers fabricated in 2016. Uniformity of the critical current satisfied our criteria for integrated circuit applications up to a JJ size of 0.5 μm2. Reliability of the Nb 9-layer process reached the 100,000 JJ circuit level. The digital circuit processes will be improved by introducing advanced fabrication machines and/or integrating new materials. Three-dimensional, analog, analog-digital monolithic and quantum computing devices are being developed based on these digital device processes.

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© 2017 by Cryogenics and Superconductivity Society of Japan (Cryogenic Association of Japan)
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