Abstract
D, T, and SR fuzzy flip-flops are proposed. Their characteristics are shown when their t-norm and s-norm are restricted to four-max-min, algebraic, bounded, drastic-logical operation system. Their electrical circuits are designed using VHDL and are synthesized to make FPGAs as target devices. The conventional JK fuzzy flip-flops are also designed in the same manner and the performances are compared with those of proposed flip-flops on a circuit simulator. The results of the simulation experiment show that the combinatorial circuit areas(without areas of latches)of D, T, SR fuzzy flip-flops are nearly 0, 1/2, 2/3 of the JK's, respectively and the delay times of D, T, SR fuzzy flip-flops are nearly 0, 2/3, 2/3 of the JK's, respectively. The areas and delay times of the proposed flip-flops increase in the first or second order with the number of their quantization bits of [0, 1], the range of fuzzy logical value. Although the functions of the proposed fuzzy flip-flops are restricted compared with those of the JK fuzzy flip-flops and are not suitable for general purpose use, they will provide the foundation for the relization of fuzzy temporary memory modules-e.g.with a multi-steps fuzzy reasoning system.
