Development of Embedded System with Camera and Median-Based Dynamic Background Subtraction Function Using High-Level Synthesis

Abstract

Hardware-based image processing is suitable for embedded systems because of its high speed and low power consumption. In addition, by using the technology of high-level synthesis, the creation of hardware can be done quickly and flexibly. In this study, we developed an embedded system with a camera that has a median-based dynamic background subtraction function. In this system, we introduced the concept of a ring buffer to run three pieces of hardware in parallel. As a result, when the image size is QVGA and the number of time-series images is 4, the maximum frame rate of the system is 194 fps. In addition, it was confirmed that the power efficiency of the system was much better than that of software processing.