Optimization of Polishing Conditions for Reducing Thickness Variation of Wafer in Double-Sided Polishing

Abstract

Silicon wafers as the most commonly used substrates for semiconductor devices are strongly required to be manufactured with superior flat surface, that is, small thickness variation to obtain high productivity and performance of the devices. The double-sided polishing (DSP) process is widely adopted as the finishing stage of the wafer manufacturing, because wafers with good surface quality and flatness can be obtained economically. To achieve further good surface flatness of wafers in DSP process with good reproducibility, we investigated a kinematics-based DSP simulation model considering the friction between wafer and pads, the friction between wafer and carrier hole and the pressure distribution on the wafer. On the basis of the simulation model, polishing conditions, in concrete, a set of rotation conditions of upper/lower platens and inner/outer gears were optimized to reduce thickness variation of wafers. DSP experiments on silicon wafers with a diameter of 300 mm revealed that the optimized condition achieved small thickness variation of wafers stably without singular shape.