Abstract
Junctions with Al2O3 and AIN barriers were fabricated through contact shadow masks (0.25mm2-size) and by a self-aligned lithography process (9×2μm2-size). The Al2O3 barrier was formed by plasma oxidation. The AlN barrier was prepared by dc reactive magnetron sputtering. Room temperature tunneling magnetoresistance (TMR) is 1.6% for the AIN junctions and up to 24% for the Al2O3 junctions. The TMR for all junctions decreases with increase of applied bias voltage and drops to half its initial value at a bias voltage between 116 mV and 437 mV. The weakest bias voltage dependence occurs for junctions with higher barrier heights, and thinner barrier thickness. Annealing at 100-200 °C leads to a 20% increase of TMR and a 40% decrease of junction resistance for the 9×2μm2 junctions, leading to a maximum TMR of 27%. Both TMR and junction resistance were increased for the AlN junctions due to annealing.
