Abstract
On V-shaped process of model based development, from upper process to lower process, methods on decomposition of design information model has not been established. This paper proposes iterative design process for refinement of design information model and stepwise verification and validation(V&V) are enforced using DSM (Dependency Structure Matrix) which expresses design information model of two layer. In this paper relation between SysML diagram, diagram element and activities to create SysML models are described on DSM and analyzed to refine models and enforce V&V process.
