Host: The Japan Society of Mechanical Engineers
Name : Proceedings of FDR2024 International Topical Workshop on Fukushima Decommissioning Research
Date : October 10, 2024 - October 13, 2024
Under a strong radiation environment such as decommissioning situation of nuclear power plants, radiation-hardened processors are required for robots and other systems. Currently, space-grade processors are available. However, currently available space-grade processors are always weak for radiation and the life-time of the space-grade processors is limited to an extremely short period. So, we have introduced triple modular redundancy (TMR) for RISC-V processor to increase the total-ionizing-dose tolerance. This paper presents a triple modular redundancy RISC-V processor design. In the RISC-V processor, majority voting operations are executed automatically at every clock cycle. The RISC-V processor was implemented onto a Cyclone-V Field Programable Gate Array (FPGA) on a DE1-SOC FPGA board. It has been confirmed that the RISC-V processor can work correctly. Additionally, the maximum operating clock frequency was measured as 64.82MHz. The FPGA’s resource usage was 45%.
