J0103-2-2 Thermo-viscoelastic analysis of warpage in multistacked CSP

Abstract

Recently, an advanced chip size packaging technology is important for developing portable electronic devices. Chip size package (CSP) is composed of IC, sealing resin and the substrate. Warp deformation occurs by temperature change due to the difference of thermal properties of each material. In this study, thermo-viscoelastic analysis of CSP using a simple theory based on a multi-layer plate theory is presented. In comparison with FEM, the method is simple and various analysis conditions such as reflow process can be considered easily. When temperature cooled down from 453K of the bonding temperature to 298K in the room temperature, the amount of warpage is predicted and compared with the results of FEM analysis.