The Proceedings of the Materials and Mechanics Conference
Online ISSN : 2424-2845
2012
Session ID : PS18
Conference information
PS18 Development of a monitoring method of residual stress in a silicon chip in a 3D stacked structure during its fabrication process
Hironori TAGORyosuke FURUYAKen SUZUKIHideo MIURA
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Abstract
The embedded strain gauges in a PQC-TEG in a silicon chip were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. In addition, the sensors were also applied to measurement of thermal residual stress in a silicon wafer caused by flip-chip bonding and the stress was successfully monitored. The sensitivity of the measurement was 1 MPa and it was validated that the amplitude of the fluctuation exceeded 100 MPa. This technique has applicability to monitoring the residual stress from front-end wafer process to packaging process.
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© 2012 The Japan Society of Mechanical Engineers
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