B303 DEVELOPMENT OF THE FAIL-SAFE SINGLE CHIP RISC-CPU BOARD

Abstract

One configuration of FS-Computer is composed of dual-CPU, dual-peripheral circuits and checking-circuits which supervise dual-CPU and peripheral circuits always running synchronously each other. We introduced the new idea of safety to implement such FS-CPU within a single chip LSI fail-safely, namely using PN-code to detect the failure of intemal circuits and so on. In this article, we address the concept of the safety of dual-CPU in a single chip and its verification.