Host: The Japan Society of Mechanical Engineers
Name : [in Japanese]
Date : October 08, 2022 - October 09, 2022
In this paper, a methodology, to identify parameters of Cauer thermal network which represents heat transfer path and power ratio of the microprocessor, is explored, targeting an embedded computing motherboard. Seven parameters are optimized from transient power curve of whole motherboard and transient junction temperature of the microprocessor, by utilizing Bayesian optimization technique. Predicted junction temperature obtained by created model matches well with measurement result.
