Hardware Implementation of Higher Rank of Self-Organizing Maps

Abstract

This paper aims to develop hardware implementation of higher-rank of self-organizing map (SOMⁿ). SOMⁿ provides a novel algorithm for multi-class learning scheme, which is expected to be a good foundation of intelligence of autonomous robots and mobile devices. For this purpose, it is important to implement SOMⁿ on small energy consuming and small size VLSIs. In this paper, we have implemented SOM² on a Filed Programmable Gate Array (FPGA). The most critical point was the number of logic elements, which restricted the size of the architecture, whereas other aspects such as memory capacity and calculation speed satisfied the required criteria. It was also shown that the logic element size problem could be avoided by using a latest FPGA device or modifying the circuit design. With considering these results, our SOM² hardware on FPGA enlarges the potential of SOMⁿ as a foundation of intelligent agents and devices.