Sequence diagrams are often used in the modular design of softwares. However, it is difficult to verify UML diagrams automatically. In this work, we develop a verification tool of sequence diagrams named SDVerifier. It converts sequence diagrams to processes in CSP, so that existing model checking tool can verify them. One of the main contributions in this work is that counter examples found in the model checking can be translated back to sequence diagrams for supporting to correct their inconsistency. We implemented the tool and conducted experiments with real world case studies.
2015 Japan Society for Software Science and Technology