Radiation-Hardened SRAMs Fabricated by Advanced Commercial SOI-Technology

Abstract

We fabricate 128-Kbit SRAMS using rad-hard circuit design based on a mixed mode 3D-simulation in a commercial SOI foundry with 0.2 μm design rules. Appropriate design increases the critical LET of single-event-upset to 45 MeV/(mg/cm²). The upset rate for the SRAM installed in equipment in a GEO orbit (M=7) is estimated to be 3.1x10^-7 upsets/device-day, which is quite an acceptable SEU hardness.