Measurement of Local Residual Stress in Si Chips Mounted by Flip Chip Technology Using Micron Scale Strain Sensors(<Special Issue>Thermal and Mechanical Reliability of Electronic Device and Mechanical Engineering)

Abstract

The change of the electronic performance of NMOS transistors caused by mechanical stress was measured by applying a four-point bending method. The change rate of the transconductance of NMOS transistors increased to about 15%/100-MPa by decreasing the gate length from 400nm to 150nm. In addition, the local residual stress in the stacked chips mounted by a flip chip technology was measured by utilizing piezoresistive stress sensors with 2-μm long gauges. The amplitude of the residual stress in the top chip was almost constant of about 220MPa regardless of the bottom bump alignment. On the other hand, the amplitude of the residual stress in the bottom chip decreased to about 80MPa depending on the relative position of bumps between the top and bottom chips.