2025 Volume 16 Issue 4 Pages 788-805
This paper proposes a hardware architecture for edge AI applications of Bayesian neural networks, enabling uncertainty evaluation in neural network inference outputs. A lightweight and highly efficient architecture originally designed for binary neural networks is extended to support Bayesian inference by introducing Monte Carlo sampling based on the Bernoulli distribution instead of the Gaussian distribution, thereby eliminating multiplication by restricting weights to binary values (-1/+1). The random number generators required for Monte Carlo sampling are also significantly downsized by sharing bitstreams. The FPGA prototype demonstrates a high simulated efficiency of 63.08 GOPS/W at 50 MHz.