Nonlinear Theory and Its Applications, IEICE
Online ISSN : 2185-4106
Special Section on Communication Sciences and Engineering
An energy-efficient dynamic branch predictor with a two-clock-cycle naïve Bayes classifier for pipelined RISC microprocessors
Itaru HidaShinya Takamaeda-YamazakiMasayuki IkebeMasato MotomuraTetsuya Asai
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Volume 8 (2017) Issue 3 Pages 235-245

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Abstract

In this paper, we propose a Bayesian branch-prediction circuit, consisting of an instruction-feature extractor and a naïve Bayes classifier (NBC), as a machine learning approach for branch prediction. A branch predictor predicts the outcome of a branch instruction by analyzing the pattern of the previous branch outcome. In other words, branch prediction can be viewed as a type of pattern recognition problem, and such problems are often solved using neural networks. A perceptron branch predictor has already been proposed as one example of a neural branch prediction architecture, which predicts the next branch outcome by using past branch history to form feature vectors. The proposed circuit is constructed by replacing the arithmetic unit (neurons) in conventional neural branch predictors with an NBC. By introducing an approximate Bayesian computation and its parallel architectures, the NBC circuit completes branch prediction within two clock cycles per instruction. This constitutes a suitable replacement for conventional branch predictors in modern pipelined reduced instruction set computing microprocessors.

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© 2017 The Institute of Electronics, Information and Communication Engineers
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