Carrier transport and thermal-aware device design of silicon nanoscale devices

Abstract

Three - dimensional transistors consisting of nanoscaled silicon channels are promising candidates as a future device structure. In nanoscale silicon, quantum effects on charged carriers and the lowering of thermal conductivity due to phonon confinement will be prominent. Therefore, devices should be designed by taking into account the effects of quantum confinement and the increase in channel temperature on electrical characteristics. In this work, an overview of the effects of quantum confinement and the larger surface-to-volume ratio on the carrier transport mechanism will be provided. Then, the channel temperature increase due to Joule heating and its impact on analog performance will be discussed.