Control of Schottky barrier height at metal/germanium interface

Abstract

To realize high performance germanium (Ge) CMOS, a low Schottky barrier height at the metal/Ge interface is required in order to reduce parasitic resistance. Therefore, we have to overcome the strong Fermi-level pining (FLP) close to valence band edge of Ge at the metal/Ge interface especially for Ge n-MOSFETs. 10 years ago, we successfully alleviated the strong FLP by inserting an ultra-thin insulator between metal and Ge based on the intrinsic metal-induced gap states model, which was reported in Applied Physics Express (APEX). In this paper, we review the background of this work and recent progress with this approach. Furthermore, we also report another new approach to alleviate the FLP recently published in APEX.