Journal of the Particle Accelerator Society of Japan
Online ISSN : 2436-1488
Print ISSN : 1349-3833
Reviews
Development of digital low level rf system
Shinichiro MICHIZONO Shozo ANAMIHiroaki KATAGIRIZhigao FANGToshihiro MATSUMOTOTakako MIURAYoshiharu YANOSeiya YAMAGUCHITetsuya KOBAYASHI
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2008 Volume 5 Issue 2 Pages 127-136

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Abstract

One of the biggest advantages of the digital low level rf (LLRF) system is its flexibility. Owing to the recent rapid progress in digital devices (such as ADCs and DACs) and telecommunication devices (mixers and IQ modulators), digital LLRF system becomes popular in these 10 years. The J–PARC linac LLRF system adopted cPCI crates and FPGA based digital feedback system. Since the LLRF control of the normal conducting cavities are more difficult than super conducting cavities due to its lower Q values, fast processing using the FPGA was the essential to the feedback control. After the successful operation of J–PARC linac LLRF system, we developed the STF (ILC test facility in KEK) LLRF system. Since the klystron drives eight cavities in STF phase 1, we modified the FPGA board. Basic configuration and the performances of these systems are summarized. The future R&D projects (ILC and ERL) is also described from the viewpoints of LLRF.

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© 2008 Particle Accelerator Society of Japan
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