Proceedings of JSPE Semestrial Meeting
2009 JSPE Spring Conference
Session ID : N16
Conference information

Enabling Solutions for planarization of 22 nm node device
*Manabu TsujimuraSatoru YamamotoJunko MineHiroyuki KandaKeiichi KurashinaTsutomu Nakada
Author information
CONFERENCE PROCEEDINGS FREE ACCESS

Details
Abstract
Development of 22 nm node devices has started. Difficult challenges of interconnects are Cu deposition on thin (2.4 nm) and conformal liners and removal of Cu and several liners without galvanic corrosion and within 6 nm planarity for ELK dielectric (k effective is 2.2). First of all, in this paper, success result of the Cu deposition direct on Ru liner without the terminal effect is reported by using dummy effect plating tool. Secondly, the planar plating with same tool is reported which shows the planar Cu plating with a special pad. In case of conventional plating, the deposition profile has a big step height depending on device pattern. This new method had no device pattern dependency. A special porous pad is mounted on the wafer. Then, the several removal methods are also introduced herein such as CMP (Chemical Mechanical Polisher), ECMP (Electrical Chemical Mechanical Polisher), ECP (Electrical Chemical Polisher), CE (Chemical Etching) and those combination technologies in accordance with the general principle of several planarization technologies. In order to clear the severe requirement on planarization in 22 nm node devices, not only CMP but also help from deposition technologies may be needed. The example of good approach from deposition to removal is reported herein.
Content from these authors
© 2009 The Japan Society for Precision Engineering
Previous article Next article
feedback
Top