Sampling rate conversion by Fourier interpolation

Manabu Inoue; Fuminori Kobayashi; Minoru Watanabe

doi:10.11499/sicep.2004.0_23_3

SICE Annual Conference 2004

DOI https://doi.org/10.11499/sicep.2004.0_23_3

Conference information

Host: The Society of Instrument and Control Engineers

Co-host: The IEEE Industrial Electronics Society, The IEEE Robotics and Automation Society, The IEEE Control Systems Society, The IEEE Systems, Man and Cybernetics Society, The Instrumentation, Systems, and Automation Society

Sampling rate conversion by Fourier interpolation

*Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe

Author information

Keywords: FPGA, digital audio

CONFERENCE PROCEEDINGS FREE ACCESS

Pages 23

Details

Abstract

New time-domain SRC using Fourier interpolation to achieve less gate count than in frequency domain is proposed and implemented by FPGA. Layout area of the proposed SRC based on a 0.35um process is 5.728mm², smaller than the conventional SRC using filters. The noise level is reduced down to the quantization error level by using several improving methods.

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